[PATCH 1/2] mmc: core: enable CMD19 tuning for DDR50 mode
From: Ulf Hansson <hidden>
Date: 2015-08-17 17:11:15
Also in:
linux-mmc
On 11 August 2015 at 10:41, Barry Song [off-list ref] wrote:
From: Weijun Yang <redacted> As SD Specifications Part1 Physical Layer Specification Version 3.01 says, CMD19 tuning is available for unlocked cards in transfer state of 1.8V signaling mode. The small difference between v3.00 and 3.01 spec means that CMD19 tuning is also available for DDR50 mode.
So what happens with cards following the 3.0 spec version, those doesn't need to support the tuning CMD right? Perhaps that needs to be addressed in this patch well!? Kind regards Uffe
quoted hunk ↗ jump to hunk
Signed-off-by: Weijun Yang <redacted> Signed-off-by: Barry Song <redacted> --- drivers/mmc/core/sd.c | 1 + drivers/mmc/host/sdhci.c | 1 + 2 files changed, 2 insertions(+)diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 4e7366a..a1ed24d 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c@@ -629,6 +629,7 @@ static int mmc_sd_init_uhs_card(struct mmc_card *card) */ if (!mmc_host_is_spi(card->host) && (card->sd_bus_speed == UHS_SDR50_BUS_SPEED || + card->sd_bus_speed == UHS_DDR50_BUS_SPEED || card->sd_bus_speed == UHS_SDR104_BUS_SPEED)) err = mmc_execute_tuning(card); out:diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 1dbe932..812c19b 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c@@ -1891,6 +1891,7 @@ static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) break; case MMC_TIMING_UHS_SDR104: + case MMC_TIMING_UHS_DDR50: break; case MMC_TIMING_UHS_SDR50: --1.9.1