[PATCH 10/18] KVM: ARM64: Add reset and access handlers for PMCCNTR_EL0 register
From: shannon.zhao at linaro.org <hidden>
Date: 2015-07-06 02:17:40
Also in:
kvm, kvmarm
Subsystem:
arm64 port (aarch64 architecture), kernel virtual machine for arm64 (kvm/arm64), the rest · Maintainers:
Catalin Marinas, Will Deacon, Marc Zyngier, Oliver Upton, Linus Torvalds
From: Shannon Zhao <redacted> Since the reset value of PMCCNTR_EL0 is UNKNOWN, use reset_unknown for its reset handler. Add access handler which emulates writing and reading PMCCNTR_EL0 register. Signed-off-by: Shannon Zhao <redacted> --- arch/arm64/kvm/sys_regs.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
index 2bcf1a0..29883df 100644
--- a/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c@@ -375,6 +375,23 @@ static bool access_pmxevcntr(struct kvm_vcpu *vcpu, return true; } +static bool access_pmccntr(struct kvm_vcpu *vcpu, + const struct sys_reg_params *p, + const struct sys_reg_desc *r) +{ + unsigned long val; + + if (p->is_write) { + val = *vcpu_reg(vcpu, p->Rt); + kvm_pmu_set_counter_value(vcpu, 31, val); + } else { + val = kvm_pmu_get_counter_value(vcpu, 31); + *vcpu_reg(vcpu, p->Rt) = val; + } + + return true; +} + /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */ #define DBG_BCR_BVR_WCR_WVR_EL1(n) \ /* DBGBVRn_EL1 */ \
@@ -590,7 +607,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { access_pmceid, reset_pmceid, PMCEID1_EL0, }, /* PMCCNTR_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b000), - trap_raz_wi }, + access_pmccntr, reset_unknown, PMCCNTR_EL0 }, /* PMXEVTYPER_EL0 */ { Op0(0b11), Op1(0b011), CRn(0b1001), CRm(0b1101), Op2(0b001), access_pmxevtyper, reset_unknown, PMXEVTYPER_EL0 },
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2.1.0