[PATCH 1/4] hvc_dcc: bind driver to core0 for reads and writes

On 06/30/2015 02:23 PM, Timur Tabi wrote:

From: Shanker Donthineni <redacted>

Some debuggers, such as Trace32 from Lauterbach GmbH, do not handle
reads/writes from/to DCC on secondary cores.  Each core has its
own DCC device registers, so when a core reads or writes from/to DCC,
it only accesses its own DCC device.  Since kernel code can run on
any core, every time the kernel wants to write to the console, it
might write to a different DCC.

In SMP mode, Trace32 only uses the DCC on core 0.  In AMP mode, it
creates multiple windows, and each window shows the DCC output
only from that core's DCC.  The result is that console output is
either lost or scattered across windows.

Selecting this option will enable code that serializes all console
input and output to core 0.  The DCC driver will create input and
output FIFOs that all cores will use.  Reads and writes from/to DCC
are handled by a workqueue that runs only core 0.

Signed-off-by: Shanker Donthineni <redacted>
Acked-by: Adam Wallis <redacted>
Signed-off-by: Timur Tabi <redacted>
---

Maybe we should look into making the console number (i.e. ttyHVC0,
ttyHVC1, etc.) correspond to the logical CPU number 0, 1, etc? We would
need some hotplug notifier to tear down and restore the console when the
CPU comes online and goes offline, but it may work out nicer than taking
the approach this patch does.

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