[PATCH v2 2/2] clk: imx: clk-imx6q: Provide initial IPU clock settings for mx6dl
From: Vladimir Zapolskiy <hidden>
Date: 2015-06-25 16:22:07
Also in:
linux-clk
Hi Fabio, On 25.06.2015 17:17, Fabio Estevam wrote:
quoted hunk ↗ jump to hunk
Currently it is not possible to use HDMI and LVDS at the same time on a imx6dl-sabresd board. Fix this usecase by setting IMX6QDL_CLK_PLL3_PFD1_540M to 540MHz and also by setting it as the parent of IMX6QDL_CLK_IPU1_SEL. Based on the configuration done in the FSL kernel. Signed-off-by: Fabio Estevam <redacted> --- Changes since v1: - None. Newly introduced. drivers/clk/imx/clk-imx6q.c | 5 +++++ 1 file changed, 5 insertions(+)diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index d046f8e..d735d8f 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c@@ -494,6 +494,11 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) clk_set_parent(clk[IMX6QDL_CLK_LDB_DI1_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); } + if (clk_on_imx6dl()) { + clk_set_rate(clk[IMX6QDL_CLK_PLL3_PFD1_540M], 540000000);
I believe here IMX6QDL_CLK_PLL3_PFD1_540M rate can be set independently of SoC flavour.
+ clk_set_parent(clk[IMX6QDL_CLK_IPU1_SEL], clk[IMX6QDL_CLK_PLL3_PFD1_540M]); + } + clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); clk_set_parent(clk[IMX6QDL_CLK_IPU1_DI1_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]); clk_set_parent(clk[IMX6QDL_CLK_IPU2_DI0_PRE_SEL], clk[IMX6QDL_CLK_PLL5_VIDEO_DIV]);
-- With best wishes, Vladimir