Thread (31 messages) 31 messages, 5 authors, 2015-05-26
STALE4035d REVIEWED: 1 (0M)
Revisions (4)
  1. v5 [diff vs current]
  2. v7 [diff vs current]
  3. v8 [diff vs current]
  4. v9 current

[PATCH v9 11/17] ARM: tegra: Enable the DFLL on the Jetson TK1

From: Mikko Perttunen <hidden>
Date: 2015-05-13 15:01:33
Also in: linux-pm, linux-tegra, lkml
Subsystem: the rest · Maintainer: Linus Torvalds

From: Tuomas Tynkkynen <redacted>

Add the board-specific properties of the DFLL for the Jetson TK1 board.
On this board, the DFLL will take control of the sd0 regulator on the
on-board AS3722 PMIC.

Signed-off-by: Tuomas Tynkkynen <redacted>
Signed-off-by: Mikko Perttunen <redacted>
Acked-by: Michael Turquette <redacted>
---
 arch/arm/boot/dts/tegra124-jetson-tk1.dts | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index bd43ed6..192111a 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
@@ -1462,7 +1462,7 @@
 				vin-ldo9-10-supply = <&vdd_5v0_sys>;
 				vin-ldo11-supply = <&vdd_3v3_run>;
 
-				sd0 {
+				vdd_cpu: sd0 {
 					regulator-name = "+VDD_CPU_AP";
 					regulator-min-microvolt = <700000>;
 					regulator-max-microvolt = <1400000>;
@@ -1694,6 +1694,13 @@
 		non-removable;
 	};
 
+	/* CPU DFLL clock */
+	clock at 0,70110000 {
+		status = "okay";
+		vdd-cpu-supply = <&vdd_cpu>;
+		nvidia,i2c-fs-rate = <400000>;
+	};
+
 	ahub at 0,70300000 {
 		i2s at 0,70301100 {
 			status = "okay";
-- 
2.3.0
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