[PATCH v8 12/18] ARM: tegra: Enable the DFLL on the Jetson TK1
From: Mikko Perttunen <hidden>
Date: 2015-03-01 12:51:27
Also in:
linux-pm, linux-tegra, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
From: Tuomas Tynkkynen <redacted> Add the board-specific properties of the DFLL for the Jetson TK1 board. On this board, the DFLL will take control of the sd0 regulator on the on-board AS3722 PMIC. Signed-off-by: Tuomas Tynkkynen <redacted> Signed-off-by: Mikko Perttunen <redacted> --- v8: - Changed dfll@ -> clock@ arch/arm/boot/dts/tegra124-jetson-tk1.dts | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts
index dbfaba0..f0888dd 100644
--- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts
+++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts@@ -1509,7 +1509,7 @@ vin-ldo9-10-supply = <&vdd_5v0_sys>; vin-ldo11-supply = <&vdd_3v3_run>; - sd0 { + vdd_cpu: sd0 { regulator-name = "+VDD_CPU_AP"; regulator-min-microvolt = <700000>; regulator-max-microvolt = <1400000>;
@@ -1737,6 +1737,13 @@ non-removable; }; + /* CPU DFLL clock */ + clock at 0,70110000 { + status = "okay"; + vdd-cpu-supply = <&vdd_cpu>; + nvidia,i2c-fs-rate = <400000>; + }; + ahub at 0,70300000 { i2s at 0,70301100 { status = "okay";
--
2.3.0