[PATCH 2/4] clk: tegra20: init NDFLASH clock to sensible rate
From: dev@lynxeye.de (Lucas Stach)
Date: 2015-01-04 20:39:18
Also in:
linux-devicetree, linux-tegra
Subsystem:
common clk framework, tegra clock driver, the rest · Maintainers:
Michael Turquette, Stephen Boyd, Prashant Gaikwad, Linus Torvalds
Set up the NAND Flash controller clock to run at 150MHz instead of the rate set by the bootloader. This is a conservative rate which also yields good performance. Signed-off-by: Lucas Stach <dev@lynxeye.de> --- drivers/clk/tegra/clk-tegra20.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c
index 41272dc..f20424d 100644
--- a/drivers/clk/tegra/clk-tegra20.c
+++ b/drivers/clk/tegra/clk-tegra20.c@@ -1063,6 +1063,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { {TEGRA20_CLK_DISP2, TEGRA20_CLK_PLL_P, 600000000, 0}, {TEGRA20_CLK_GR2D, TEGRA20_CLK_PLL_C, 300000000, 0}, {TEGRA20_CLK_GR3D, TEGRA20_CLK_PLL_C, 300000000, 0}, + {TEGRA20_CLK_NDFLASH, TEGRA20_CLK_PLL_P, 150000000, 0}, {TEGRA20_CLK_CLK_MAX, TEGRA20_CLK_CLK_MAX, 0, 0}, /* This MUST be the last entry */ };
--
2.1.0