[PATCH V2] clk: mxs: Fix invalid 32-bit access to frac registers

From
Marek Vasut <marex@denx.de>
Date
2015-01-22 00:50:16
Also in
lkml
Reply to
Zhi Li, 2015-01-21
On Wednesday, January 21, 2015 at 05:16:03 PM, Zhi Li wrote:
On Sun, Dec 28, 2014 at 4:26 AM, Stefan Wahren [off-list ref] wrote:
quoted
According to i.MX23 and i.MX28 reference manual the fractional
clock control registers must be addressed by byte instructions.
I don't think mx23 and mx28 have such limitation. I will double check
with IC team about this.
RTL is generated from a xml file. All registers implement is unified.
I don't think only clock control register have such limitation and
other registers not.
Hi,

Section 10.8.24 in the MX28 datasheet (Fractional Clock Control Register 0) 
states otherwise, but maybe the documentation is simply not matching the
silicon.

Here's a quote:
"
This register controls the 9-phase fractional clock dividers. The fractional 
clock frequencies are a product of the values in these registers. NOTE: This 
register can only be addressed by byte instructions. Addressing word or half-
word are not allowed.
"

I also recall seeing weird behavior when these registers were accessed by word
access in U-Boot, so I believe the datasheet is correct.

Best regards,
Marek Vasut
Thread (12 messages) 12 messages, 5 authors, last reply 2015-01-29
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