Dear Sebastian,

On Wed, 7 Jan 2015 06:11:58 -0800
Sebastian Hesselbarth [off-list ref] wrote:

On 31.12.2014 09:57, Jisheng Zhang wrote:

quoted

The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.

Signed-off-by: Jisheng Zhang <redacted>
Cc: stable at vger.kernel.org # 3.16+
---
  drivers/clk/berlin/bg2q.c | 1 -
  1 file changed, 1 deletion(-)

diff --git a/drivers/clk/berlin/bg2q.c b/drivers/clk/berlin/bg2q.c
index 21784e4..440ef81 100644
--- a/drivers/clk/berlin/bg2q.c
+++ b/drivers/clk/berlin/bg2q.c

@@ -285,7 +285,6 @@ static const struct berlin2_gate_data bg2q_gates[]

__initconst = { { "pbridge",	"perif",	15,
CLK_IGNORE_UNUSED }, { "sdio",	"perif",	16,
CLK_IGNORE_UNUSED }, { "nfc",	"perif",	18 },

The nfc here is really confusing, we call it as nfccore internally. Is it better
to rename it as nfccore?

quoted

-	{ "smemc",	"perif",	19 },

Jisheng,

if bit 19 is for nfc, how does that work out with bit 18 which is
still assigned to nfc? Can you re-evaluate clkenable registers for

bit 19 is for nfcEcc, the "io" clock; bit 18 is for nfcCore, the "core" clock.

BG2Q and fix it up accordingly? I'd suggest to still disable as many

I'll recheck the clk driver for BG2Q.

Thanks very much,
Jisheng