On Wed, Oct 29, 2014 at 10:16 PM, Arnd Bergmann [off-list ref] wrote:

On Wednesday 29 October 2014 22:09:00 Y Vo wrote:

quoted

Hi Arnd,

Per Linus, shall we hold this driver until the GIC submission complete
? Or we will send the version without access GIC to read status in
case the GPIO is configured IRQ ?

I'm fine with it either way.

quoted

+static int xgene_gpio_sb_get(struct gpio_chip *gc, u32 gpio)
+{
+       struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
+       struct xgene_gpio_sb *chip = to_xgene_gpio_sb(mm_gc);
+       u32 data;
+
+       data = ioread32(mm_gc->regs + MPA_GPIO_IN_ADDR);
+
+       return (data &  GPIO_MASK(gpio)) ? 1 : 0;
+}

This would be actually broken, right? Maybe it's better to change the
driver so that it refuses to map GPIO lines that are hardwired to
the interrupt controller, until we can support that.

It still works if they are configure as GPIO.
Do you have any reference to resolve it ?