[PATCH v7 2/5] phy: add a driver for the Rockchip SoC internal USB2.0 PHY

From
Doug Anderson <dianders@chromium.org>
Date
2014-12-15 18:12:24
Also in
linux-devicetree, lkml
Reply to
Yunzhi Li, 2014-12-12
Yunzhi,

On Fri, Dec 12, 2014 at 7:07 AM, Yunzhi Li [off-list ref] wrote:
This patch to add a generic PHY driver for ROCKCHIP usb PHYs,
currently this driver can support RK3288. The RK3288 SoC have
three independent USB PHY IPs which are all configured through a
set of registers located in the GRF (general register files)
module.

Signed-off-by: Yunzhi Li <redacted>

---

Changes in v7:
- Accept Kishon's comments to use phandle args to find a phy
  struct directly and get rid of using a custom of_xlate
  function.

Changes in v6:
- Rename SIDDQ_MSK to SIDDQ_WRITE_ENA.

Changes in v5: None
Changes in v4:
- Get number of PHYs from device tree.
- Model each PHY as subnode of the phy provider node.

Changes in v3:
- Use BIT macro instead of bit shift ops.
- Rename the config entry to PHY_ROCKCHIP_USB.

 drivers/phy/Kconfig            |   7 ++
 drivers/phy/Makefile           |   1 +
 drivers/phy/phy-rockchip-usb.c | 158 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 166 insertions(+)
 create mode 100644 drivers/phy/phy-rockchip-usb.c
On rk3288-pinky (on a 3.14 tree with backports), I can confirm that
this properly gets us into low power at suspend time.

Tested-by: Doug Anderson <dianders@chromium.org>
Thread (15 messages) 15 messages, 4 authors, last reply 2015-02-19
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