[PATCH 1/5] DT: phy: qcom: Add PCIe PHY devicetree bindings
From: Stanimir Varbanov <hidden>
Date: 2014-12-12 17:17:10
Also in:
linux-arm-msm, linux-devicetree, linux-pci, lkml
Subsystem:
arm/qualcomm mailing list, generic phy framework, open firmware and flattened device tree bindings, the rest · Maintainers:
Vinod Koul, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
Document Qualcomm PCIe PHY devicetree bindings. Signed-off-by: Stanimir Varbanov <redacted> --- .../devicetree/bindings/phy/qcom-pcie-phy.txt | 62 ++++++++++++++++++++ 1 files changed, 62 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt
new file mode 100644
index 0000000..f53eaf3
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom-pcie-phy.txt@@ -0,0 +1,62 @@ +* Qualcomm PCIe PHY controller + +PCIe PHY nodes are defined to describe on-chip SATA Physical layer controllers. +Each SATA PHY controller should have its own node. + +- compatible: + Usage: required + Value type: <stringlist> + Definition: Value should contain "qcom,pcie-phy" + +- reg: + Usage: required + Value type: <prop-encoded-array> + Definition: Offset and length of the PCIe PHY registers + +- #phy-cells: + Usage: required + Value type: <u32> + Definition: Must be zero + +- clocks: + Usage: required + Value type: <prop-encoded-array> + Definition: A list of phandles and clock specifier pair, one + for each entry in clock-names property + +- clock-names: + Usage: required + Value type: <stringlist> + Definition: Must be "core" for PHY core clock + +- resets: + Usage: required + Value type: <phandle> + Definition: List of phandle and reset specifier pairs as listed + in reset-names property + +- reset-names: + Usage: required + Value type: <stringlist> + Definition: Should contain "phy" for PHY reset + +- <name>-supply: + Usage: required + Value type: <phandle> + Definition: List of phandles to the supply regulators + - "vdda" analog Vdd supply + - "vdda_pll" analog Vdd PLL supply + +* Example + + pciephy0: phy at fc526000 { + compatible = "qcom,pcie-phy"; + reg = <0xfc526000 0x1000>; + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "core"; + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + vdda-supply = <&pma8084_l3>; + vdda_pll-supply = <&pma8084_l12>; + #phy-cells = <0>; + };
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1.7.0.4