+               of_node_put(cpu_node);
+               if (found)
+                       break;
+       }
+
+       if (found) {
+               drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_KERNEL);
+               if (drv)
+                       *spm_cpu = cpu;
+       }
+
+       return drv;
+}
+
+static const struct of_device_id spm_match_table[] = {
+       { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
+         .data = &spm_reg_8974_8084_cpu },
+       { .compatible = "qcom,apq8084-saw2-v2.1-cpu",
+         .data = &spm_reg_8974_8084_cpu },
+       { .compatible = "qcom,apq8064-saw2-v1.1-cpu",
+         .data = &spm_reg_8064_cpu },
+       { },
+};
+
+static const struct qcom_cpu_pm_ops lpm_ops = {
+       .standby = qcom_cpu_standby,
+       .spc = qcom_cpu_spc,
+};
+
+static int spm_dev_probe(struct platform_device *pdev)
+{
+       struct spm_driver_data *drv;
+       struct resource *res;
+       const struct of_device_id *match_id;
+       void __iomem *addr;
+       int cpu = -EINVAL;
+       static bool cpuidle_drv_init;
+       const struct platform_device_info qcom_cpuidle_info = {
+               .name   = "qcom_cpuidle",
+               .id     = -1,
+               .data = &lpm_ops,
+               .size_data = sizeof(lpm_ops),
+       };
+
+       drv = spm_get_drv(pdev, &cpu);
+       if (!drv || cpu < 0)
+               return -EINVAL;
+
+       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+       drv->reg_base = devm_ioremap_resource(&pdev->dev, res);
+       if (IS_ERR(drv->reg_base))
+               return PTR_ERR(drv->reg_base);
+
+       match_id = of_match_node(spm_match_table, pdev->dev.of_node);
+       if (!match_id)
+               return -ENODEV;
+
+       drv->reg_data = match_id->data;
+
+       /* Write the SPM sequences first.. */
+       addr = drv->reg_base + drv->reg_data->reg_offset[SPM_REG_SEQ_ENTRY];
+       __iowrite32_copy(addr, drv->reg_data->seq,
+                       ARRAY_SIZE(drv->reg_data->seq) / 4);
+
+       /*
+        * ..and then the control registers.
+        * On some SoC's if the control registers are written first and if the
+        * CPU was held in reset, the reset signal could trigger the SPM state
+        * machine, before the sequences are completely written.
+        */
+       spm_register_write(drv, SPM_REG_CFG, drv->reg_data->spm_cfg);
+       spm_register_write(drv, SPM_REG_DLY, drv->reg_data->spm_dly);
+       spm_register_write(drv, SPM_REG_PMIC_DLY, drv->reg_data->pmic_dly);
+
+       spm_register_write(drv, SPM_REG_PMIC_DATA_0,
+                               drv->reg_data->pmic_data[0]);
+       spm_register_write(drv, SPM_REG_PMIC_DATA_1,
+                               drv->reg_data->pmic_data[1]);
+
+       /*
+        * Ensure all observers see the above register writes before the
+        * cpuidle driver is allowed to use the SPM.
+        */
+       wmb();
+       per_cpu(cpu_spm_drv, cpu) = drv;
+
+       if (!cpuidle_drv_init) {
+               platform_device_register_full(&qcom_cpuidle_info);
+               cpuidle_drv_init = true;
+       }
+
+       return 0;
+}
+
+static struct platform_driver spm_driver = {
+       .probe = spm_dev_probe,
+       .driver = {
+               .name = "saw",
+               .of_match_table = spm_match_table,
+       },
+};
+
+module_platform_driver(spm_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("SAW power controller driver");
+MODULE_ALIAS("platform:saw");

diff --git a/include/soc/qcom/pm.h b/include/soc/qcom/pm.h
new file mode 100644
index 0000000..d9a56d7
--- /dev/null
+++ b/include/soc/qcom/pm.h

@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2009-2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#ifndef __QCOM_PM_H
+#define __QCOM_PM_H
+
+enum pm_sleep_mode {
+       PM_SLEEP_MODE_STBY,
+       PM_SLEEP_MODE_RET,
+       PM_SLEEP_MODE_SPC,
+       PM_SLEEP_MODE_PC,
+       PM_SLEEP_MODE_NR,
+};
+
+struct qcom_cpu_pm_ops {
+       int (*standby)(void *data);
+       int (*spc)(void *data);
+};
+
+#endif  /* __QCOM_PM_H */
--

2.1.0


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