[PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock

On Sat, Sep 06, 2014 at 02:45:10PM +0800, Chen-Yu Tsai wrote:

The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.

This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.

This patch adds a proper divider table for it, so the correct
clock rate can be calculated.

Signed-off-by: Chen-Yu Tsai <redacted>

Applied, thanks!

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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