On Sat, Sep 27, 2014 at 04:49:55PM +0800, Chen-Yu Tsai wrote:
quoted hunk
The DMA controller requires AHB1 bus clock to be clocked from PLL6.
Signed-off-by: Chen-Yu Tsai <redacted>
---
arch/arm/boot/dts/sun6i-a31.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index caf879d..d7845d3 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -353,6 +353,11 @@
clocks = <&ahb1_gates 6>;
resets = <&ahb1_rst 6>;
#dma-cells = <1>;
+
+ /* DMA controller requires AHB1 clocked from PLL6 */
+ assigned-clocks = <&ahb1>;
+ assigned-clock-parents = <&pll6 0>;
+ assigned-clock-rates = <200000000>;
Again, I don't think we need the rate change, and that it's the right
place to put it.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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