[linux-sunxi] Re: [PATCH 1/7] clk: sunxi: Add post clk divider for factor clocks

Hi,

On Sat, Sep 13, 2014 at 10:43 PM, Emilio L?pez [off-list ref] wrote:

Hi,

El 06/09/14 a las 07:47, Chen-Yu Tsai escibi?:

quoted

Some factor clocks, mostly PLLs, have an extra fixed divider just before
the clock output. Add an option to the factor clk driver config data to
specify this divider.

Signed-off-by: Chen-Yu Tsai <redacted>
---
  drivers/clk/sunxi/clk-factors.c | 3 +++
  drivers/clk/sunxi/clk-factors.h | 1 +
  2 files changed, 4 insertions(+)

diff --git a/drivers/clk/sunxi/clk-factors.c

b/drivers/clk/sunxi/clk-factors.c
index 2057c8a..435111d 100644

--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c

@@ -64,6 +64,9 @@ static unsigned long clk_factors_recalc_rate(struct

clk_hw *hw,
        /* Calculate the rate */
        rate = (parent_rate * (n + config->n_start) * (k + 1) >> p) / (m +
1);

+       if (config->post_div)
+               rate /= config->post_div;
+
        return rate;
  }

diff --git a/drivers/clk/sunxi/clk-factors.h

b/drivers/clk/sunxi/clk-factors.h
index d2d0efa..ce70c65 100644

--- a/drivers/clk/sunxi/clk-factors.h
+++ b/drivers/clk/sunxi/clk-factors.h

@@ -16,6 +16,7 @@ struct clk_factors_config {
        u8 pshift;
        u8 pwidth;
        u8 n_start;
+       u8 post_div;
  };

  struct clk_factors {

For the record, I liked your solution on[1] more, as it's in line with what
we're doing on the other sunxi platforms, instead of adding features in
factors to cover for some cases. But it's your and Maxime's call, as I
haven't written any of the sun6i code so far.

I'm OK either way. It's really up to Maxime whether he likes the DT
representation.

Cheers!

Emilio

[1] https://patchwork.kernel.org/patch/4228541/