[PATCH 3/7] clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider

Hi,

On Fri, Sep 12, 2014 at 5:02 AM, Maxime Ripard
[off-list ref] wrote:

Hi,

On Sat, Sep 06, 2014 at 06:47:24PM +0800, Chen-Yu Tsai wrote:

quoted

This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <redacted>

It looks fine, but I'd rather see this in a separate file, especially
since we don't seem to have any order dependency.

Sorry, just to be clear, separate file under clk/sunxi?

This cannot be in a separate file, as it shares a spinlock with apb1
divider. They share the same register.

We could move apb1 out though. But i would prefer to do that when
we split out all the clocks into individual OF_CLK_DECLAREs.

ChenYu