________________________________________
From: Daniel Lezcano [daniel.lezcano at linaro.org]
Sent: Wednesday, September 17, 2014 8:22 PM
To: Shilimkar, Santosh; Menon, Nishanth; Tony Lindgren; Kristo, Tero; Paul Walmsley
Cc: Kevin Hilman; linux-arm-kernel at lists.infradead.org; linux-omap at vger.kernel.org; linux-kernel at vger.kernel.org; J, KEERTHY; Beno?t Cousson
Subject: Re: [PATCH 08/10] ARM: OMAP5/DRA7: PM: cpuidle MPU CSWR support

On 09/17/2014 04:20 PM, Shilimkar, Santosh wrote:

Sorry for the format. Emailing from webmail.
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[ ... ]

quoted

+     cx->mpu_state_vote++;
+     if (cx->mpu_state_vote == num_online_cpus()) {
+             pwrdm_set_logic_retst(mpu_pd, cx->mpu_logic_state);
+             omap_set_pwrdm_state(mpu_pd, cx->mpu_state);
+     }
+     raw_spin_unlock_irqrestore(&mpu_lock, flag);
+
+     omap4_enter_lowpower(dev->cpu, cx->cpu_state);
+
+     raw_spin_lock_irqsave(&mpu_lock, flag);
+     if (cx->mpu_state_vote == num_online_cpus())
+             omap_set_pwrdm_state(mpu_pd, PWRDM_POWER_ON);
+     cx->mpu_state_vote--;
+     raw_spin_unlock_irqrestore(&mpu_lock, flag);

I am not sure that will work. What happens if a cpu exits idle and then
re-enter idle immediately ?

[Santosh] It works and that case is already taken care. CPU exist the idle and then votes
out for cluster state and if it reenters with the right targeted state, the cluster state would
be picked.

It isn't possible to have one cpu disabling the coherency, while the
other one is looking for a lock ? Or eg. cpu0 is on WFI then cpu1 is the
last entering idle. While cpu1 is entering 'lowpower', cpu0 exits the
wfi check the state vote and set the power domain on. In the meantime
cpu1 disables the coherency and cpu0 decrease the vote and release the
lock. Could be possible there is a very small racy window here ?

[Santosh] The coherency isn't disable by CPU. Thats actually taken care by
hardware. CPU takes it own power domain down and takes itself out of
coherency. The Coherency is always ON as long as there is a CPU ON
and SMP bit on that CPU is enabled.

The scenario, you mentioned can never happen on this hardware thanks
to the inbuilt smart hardware.

If you have more questions, lets discuss. I am around here at connect. ;-)

Regards,
Santosh