On Fri, Aug 29, 2014 at 10:53:51AM +0800, Shawn Guo wrote:

On Fri, Aug 29, 2014 at 09:49:50AM +0800, Shengjiu Wang wrote:

quoted

On Thu, Aug 28, 2014 at 04:44:21PM +0800, Shawn Guo wrote:

quoted

On Tue, Aug 26, 2014 at 11:35:12PM +0800, Shawn Guo wrote:

quoted

The i.MX6 clock drivers currently hard-code all PLL clocks sourcing from
OSC24M without BYPASS support.  The patch adds BYPASS and BYPASS_CLK_SRC
selection for PLL clocks as per Figure 10-3. Primary Clock Generation
in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as
mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock
after BYPASS mux.

Signed-off-by: Shawn Guo <redacted>

Shengjiu,

Can you please test if this BYPASS support works good for your ESAI use
case?

Shawn

Yes, after test, one issue found. Please check.

-static const char *pll_bypass_src_sels[] = { "osc", "anaclk1", "anaclk2", "dummy", };
+static const char *pll_bypass_src_sels[] = { "osc", "lvds1_in", "lvds2_in", "dummy", };

Ah, yes.  I will fix my code.

So doest that mean with the above fix, we can now source 24.576MHz from
board directly to ESAI with audio PLL in bypass mode?

Shawn

Otherwise I still need to do some step in below to source the clock to ESAI.

        clk_set_parent(pll4_bypass_src, lvds2_in);
        clk_set_parent(pll4_bypass, pll4_bypass_src);
        clk_set_rate(pll4_audio_div, 24576000);
        clk_set_rate(esai_extal, 24576000);

I think it is what we can expect, right? if yes, the patch is ok for ESAI.

wang shengjiu