[PATCH] mmc: sdhci-sirf: fix 8bit width enable by overwriting set_bus_width
From: Ulf Hansson <hidden>
Date: 2014-08-19 11:22:59
Also in:
linux-mmc
On 19 August 2014 09:07, Barry Song [off-list ref] wrote:
quoted hunk ↗ jump to hunk
From: Minda Chen <redacted> 8bit-width enable bit of CSR MMC hosts is 3, while stardard hosts use bit 5. this patch fixes the functionality of 8bit transfer in CSR mmc controllers and improve performance for mmc0 a lot. Signed-off-by: Minda Chen <redacted> Signed-off-by: Barry Song <redacted> --- drivers/mmc/host/sdhci-sirf.c | 27 ++++++++++++++++++++++++++- 1 file changed, 26 insertions(+), 1 deletion(-)diff --git a/drivers/mmc/host/sdhci-sirf.c b/drivers/mmc/host/sdhci-sirf.c index 1700453..376f45f 100644 --- a/drivers/mmc/host/sdhci-sirf.c +++ b/drivers/mmc/host/sdhci-sirf.c@@ -15,6 +15,8 @@ #include <linux/mmc/slot-gpio.h> #include "sdhci-pltfm.h" +#define SDHCI_SIRF_8BITBUS BIT(3) + struct sdhci_sirf_priv { struct clk *clk; int gpio_cd;@@ -27,10 +29,33 @@ static unsigned int sdhci_sirf_get_max_clk(struct sdhci_host *host) return clk_get_rate(priv->clk); } +static void sdhci_sirf_set_bus_width(struct sdhci_host *host, int width) +{ + u8 ctrl; + + ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); + if (width == MMC_BUS_WIDTH_8) { + ctrl &= ~SDHCI_CTRL_4BITBUS; + /* + * 8bit-width enable bit of CSR MMC hosts is 3, + * while stardard hosts use bit 5 + */
Don't you need to check for host->version >= SDHCI_SPEC_300 here as well?
+ ctrl |= SDHCI_SIRF_8BITBUS;
+ } else {
+ if (host->version >= SDHCI_SPEC_300)
+ ctrl &= ~SDHCI_SIRF_8BITBUS;
+ if (width == MMC_BUS_WIDTH_4)
+ ctrl |= SDHCI_CTRL_4BITBUS;
+ else
+ ctrl &= ~SDHCI_CTRL_4BITBUS;
+ }
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+}
+
static struct sdhci_ops sdhci_sirf_ops = {
.set_clock = sdhci_set_clock,
.get_max_clock = sdhci_sirf_get_max_clk,
- .set_bus_width = sdhci_set_bus_width,
+ .set_bus_width = sdhci_sirf_set_bus_width,
.reset = sdhci_reset,
.set_uhs_signaling = sdhci_set_uhs_signaling,
};
--
2.0.4Kind regards Uffe