[PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code
From: dinguyen at opensource.altera.com <hidden>
Date: 2014-08-14 15:51:31
Also in:
linux-devicetree
Subsystem:
the rest · Maintainer:
Linus Torvalds
Possibly related (same subject, not in this thread)
- 2014-08-14 · Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code · Pavel Machek <hidden>
- 2014-08-14 · Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code · Dinh Nguyen <hidden>
- 2014-08-14 · Re: [PATCH 3/3] ARM: dts: socfpga: memreserve first 4KB for SMP code · Pavel Machek <hidden>
From: Dinh Nguyen <redacted> The SOCFPGA's SMP code uses 0x0 for as the location for the trampoline to bring secondary cores online. This patch adds a /memreserve/ section to reserve the first 4K for the SMP trampoline code. Signed-off-by: Dinh Nguyen <redacted> --- arch/arm/boot/dts/socfpga_arria5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 + 2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi
index 468fc4c..73b939e 100644
--- a/arch/arm/boot/dts/socfpga_arria5.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria5.dtsi@@ -15,6 +15,7 @@ */ /dts-v1/; +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / {
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi
index 33cad8b..f0785f0 100644
--- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi
+++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi@@ -16,6 +16,7 @@ */ /dts-v1/; +/memreserve/ 0x00000000 0x0001000; #include "socfpga.dtsi" / {
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2.0.3