On Mon, Jun 30, 2014 at 07:38:13PM +0100, Stephen Warren wrote:

On 06/30/2014 11:43 AM, Mark Rutland wrote:

quoted

On Sat, Jun 28, 2014 at 02:02:28AM +0100, Thierry Reding wrote:

quoted

From: Thierry Reding <redacted>

The Legacy Interrupt Controller found on NVIDIA Tegra SoCs is used by
the AVP coprocessor and can also serve as a backup for the ARM Cortex
CPU's local interrupt controller (GIC).

The LIC is subdivided into multiple identical units, each handling 32
possible interrupt sources.

Signed-off-by: Thierry Reding <redacted>
---
Changes in v2:
- new patch

 .../interrupt-controller/nvidia,tegra20-ictlr.txt     | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt

diff --git a/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt
new file mode 100644
index 000000000000..c695ec713740
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/nvidia,tegra20-ictlr.txt

@@ -0,0 +1,19 @@
+NVIDIA Tegra Legacy Interrupt Controller
+
+The legacy interrupt controller is divided into units that serve 32 interrupts
+each. Tegra20 implements four units, whereas Tegra30 and later implement five.
+
+Required properties:
+- compatible: "nvidia,tegra<chip>-ictlr"

And valid <chip> values are?

Do you really want us to edit every single binding every time a new chip
comes out? Surely just relying NVIDIA's published chip names is fine?

While I am not a fan of wildcards in documentation, if you feel this is
clear as is then feel free to leave it as-is. The example is probably
sufficient.

Mark.