[PATCH v2 6/6] ARM: dts: exynos4: Add nodes for L2 cache controller
From: Tomasz Figa <hidden>
Date: 2014-06-25 13:39:37
Also in:
linux-omap, linux-samsung-soc, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
This patch adds device tree nodes for L2 cache controller present on Exynos4 SoCs. Signed-off-by: Tomasz Figa <redacted> --- arch/arm/boot/dts/exynos4210.dtsi | 9 +++++++++ arch/arm/boot/dts/exynos4x12.dtsi | 14 ++++++++++++++ 2 files changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index ee3001f..99970ab 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi@@ -54,6 +54,15 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller at 10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <2 2 1>; + }; + gic: interrupt-controller at 10490000 { cpu-offset = <0x8000>; };
diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi
index c5a943d..ddffefe 100644
--- a/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/arch/arm/boot/dts/exynos4x12.dtsi@@ -60,6 +60,20 @@ reg = <0x10023CA0 0x20>; }; + l2c: l2-cache-controller at 10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + clock: clock-controller at 10030000 { compatible = "samsung,exynos4412-clock"; reg = <0x10030000 0x20000>;
--
1.9.3