Thread (122 messages) 122 messages, 15 authors, 2014-05-09
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[PATCH 68/97] ARM: l2c: sti: remove cache size override

From: Maxime Coquelin <hidden>
Date: 2014-05-09 17:54:58


On 05/09/2014 06:10 PM, Srinivas Kandagatla wrote:
Hi Maxime,
On 09/05/14 07:53, Maxime Coquelin wrote:
quoted
Hi Srini,

On 04/29/2014 08:48 AM, Srinivas Kandagatla wrote:
quoted
Hi Russell,
Thankyou for the patch,

The only issue I see is, on most of the STi SOCs the default value for
AUXCTRL register is 0x0, so the waysize is not set.
I checked all the ARM SoCs we support currently.
Only STiH416 has its reset value at 0x0.
quoted
The way size is different on some SOCs in the same series.

Where is the way-size mentioned in this new style?
Then, I think it should be the role of the bootloaders to set it for
STiH416 (I have been told U-Boot already does it).
Does it sound acceptable for you?
That's great, so the gdb startup scripts should takecare of it too.
It's already in my ToDo list!

Thanks,
Maxime

Thanks,
srini
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