[PATCH 10/12] drivers: clk: st: STiH407: Support for clockgenA9
STALE4529d
From: Gabriel FERNANDEZ <hidden>
Date: 2014-05-12 16:11:37
Also in:
linux-devicetree, lkml
Subsystem:
common clk framework, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Linus Torvalds
Revision v1 of 4 in this series.
Revisions (4)
- v1 current
- resend [diff vs current]
- v2 [diff vs current]
- v3 [diff vs current]
The patch added support for DT registration of ClockGenA9 It includes c32 type PLL. Signed-off-by: Gabriel Fernandez <redacted> Signed-off-by: Olivier Bideau <redacted> --- drivers/clk/st/clkgen-pll.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index cb4e5b6..2c6bba7 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c@@ -216,6 +216,18 @@ static struct clkgen_pll_data st_pll3200c32_407_c0_1 = { .ops = &stm_pll3200c32_ops, }; +static struct clkgen_pll_data st_pll3200c32_407_a9 = { + /* 407 A9 */ + .pdn_status = CLKGEN_FIELD(0x1a8, 0x1, 0), + .locked_status = CLKGEN_FIELD(0x87c, 0x1, 0), + .ndiv = CLKGEN_FIELD(0x1b0, C32_NDIV_MASK, 0), + .idf = CLKGEN_FIELD(0x1a8, C32_IDF_MASK, 25), + .num_odfs = 1, + .odf = { CLKGEN_FIELD(0x1b0, C32_ODF_MASK, 8) }, + .odf_gate = { CLKGEN_FIELD(0x1ac, 0x1, 28) }, + .ops = &stm_pll3200c32_ops, +}; + /** * DOC: Clock Generated by PLL, rate set and enabled by bootloader *
@@ -618,6 +630,10 @@ static struct of_device_id c32_pll_of_match[] = { .compatible = "st,stih407-plls-c32-c0_1", .data = &st_pll3200c32_407_c0_1, }, + { + .compatible = "st,stih407-plls-c32-a9", + .data = &st_pll3200c32_407_a9, + }, {} };
--
1.9.1