On Fri, Apr 04, 2014 at 12:57:28PM -0700, Stephen Boyd wrote:
quoted hunk ↗ jump to hunk
The Krait L1/L2 error reporting hardware is made up a per-CPU
interrupt for the L1 cache and a SPI interrupt for the L2.
Cc: Lorenzo Pieralisi <redacted>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <redacted>
Cc: <redacted>
Signed-off-by: Stephen Boyd <redacted>
---
Documentation/devicetree/bindings/arm/cache.txt | 48 ++++++++++++++++++++++++-
1 file changed, 47 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
index b90fcc7c53cf..d7357e777399 100644
--- a/Documentation/devicetree/bindings/arm/cache.txt
+++ b/Documentation/devicetree/bindings/arm/cache.txt
Right, that's http://www.spinics.net/lists/arm-kernel/msg308540.html
So whoever picks those patches up, Lorenzo's doc needs to be in his tree
first too.
How about I review the EDAC part and an arm maintainer picks the whole
series up? Would that be easier, logistically?
--
Regards/Gruss,
Boris.
Sent from a fat crate under my desk. Formatting is fine.
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