On Wed, Mar 26, 2014 at 02:28:42PM +0000, Rob Herring wrote:

On Wed, Mar 19, 2014 at 6:12 PM, Tanmay Inamdar [off-list ref] wrote:

quoted

This patch adds the device tree nodes for APM X-Gene PCIe controller and
PCIe clock interface. Since X-Gene SOC supports maximum 5 ports, 5 dts
nodes are added.

[snip]

quoted

+               pcie0: pcie at 1f2b0000 {
+                       status = "disabled";
+                       device_type = "pci";
+                       compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
+                       #interrupt-cells = <1>;
+                       #size-cells = <2>;
+                       #address-cells = <3>;
+                       reg = < 0x00 0x1f2b0000 0x0 0x00010000   /* Controller registers */
+                               0xe0 0xd0000000 0x0 0x00200000>; /* PCI config space */

Where is the right place for config space? This binding has it here
and others have it in ranges. Given that config space type is defined
for ranges, I would think that is the right place. But Liviu's patches
do not process config space entries in ranges. Perhaps we need a
config space resource populated in the bridge struct.

Rob,

Have a look at the discussion between Will and Arnd on the subject of virtual PCI
host controller for arm 32bit. My understanding is that config space is described
via reg entries.

See here: http://archive.arm.linux.org.uk/lurker/message/20140205.190947.b3c3e464.en.html

Best regards,
Liviu

Rob

quoted

+                       reg-names = "csr", "cfg";
+                       ranges = <0x01000000 0x00 0x00000000 0xe0 0x00000000 0x00 0x00010000   /* io */
+                                 0x02000000 0x00 0x10000000 0xe0 0x10000000 0x00 0x80000000>; /* mem */

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