[PATCH v5 09/14] ARM: mvebu: Allow to power down L2 cache controller in idle mode
From: Gregory CLEMENT <hidden>
Date: 2014-03-25 22:51:22
Also in:
linux-pm, lkml
Subsystem:
arm port, arm/marvell kirkwood and armada 370, 375, 38x, 39x, xp, 3700, 7k/8k, cn9130 soc support, the rest · Maintainers:
Russell King, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Linus Torvalds
This commit adds a function which adjusts the PMSU configuration to automatically power down the L2 and coherency fabric when we enter a certain idle state. This feature is part of the Power Management Service Unit of the Armada 370 and Armada XP SoCs. Signed-off-by: Gregory CLEMENT <redacted> --- arch/arm/mach-mvebu/pmsu.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-mvebu/pmsu.c b/arch/arm/mach-mvebu/pmsu.c
index 865bcb651e01..3cfb56f980f3 100644
--- a/arch/arm/mach-mvebu/pmsu.c
+++ b/arch/arm/mach-mvebu/pmsu.c@@ -30,8 +30,15 @@ static void __iomem *pmsu_reset_base; #define PMSU_BASE_OFFSET 0x100 #define PMSU_REG_SIZE 0x1000 -#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) -#define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8) +/* PMSU MP registers */ +#define PMSU_BOOT_ADDR_REDIRECT_OFFSET(cpu) ((cpu * 0x100) + 0x124) + +/* PMSU reset registers */ +#define PMSU_RESET_CTL_OFFSET(cpu) (cpu * 0x8) + +/* PMSU fabric registers */ +#define L2C_NFABRIC_PM_CTL 0x4 +#define L2C_NFABRIC_PM_CTL_PWR_DOWN BIT(20) static struct of_device_id of_pmsu_table[] = { {
@@ -111,4 +118,17 @@ static int __init armada_370_xp_pmsu_init(void) return 0; } +static void armada_370_xp_pmsu_enable_l2_powerdown_onidle(void) +{ + u32 reg; + + if (pmsu_mp_base == NULL) + return; + + /* Enable L2 & Fabric powerdown in Deep-Idle mode - Fabric */ + reg = readl(pmsu_mp_base + L2C_NFABRIC_PM_CTL); + reg |= L2C_NFABRIC_PM_CTL_PWR_DOWN; + writel(reg, pmsu_mp_base + L2C_NFABRIC_PM_CTL); +} + early_initcall(armada_370_xp_pmsu_init);
--
1.8.1.2