On 03/03/14 11:13, S?ren Brinkmann wrote:

On Mon, 2014-03-03 at 08:07PM +0100, Gerhard Sittig wrote:

quoted

On Mon, Mar 03, 2014 at 09:35 -0800, S?ren Brinkmann wrote:

quoted

It would be nice if we could use the logic provided in the mux, div etc
primitives independently of how the HW is accessed and what is
necessary to shift and mask those register values around, right? I
mean, at then end we want to model a clk-(div|mux) and not a
clk-(div|mux) which has only a single, memory-mapped control register,
that does not overlap with other things, ...

Did you lookup the ll_ops discussion in the thread that
originated from
http://article.gmane.org/gmane.linux.ports.arm.kernel/289895 and
did you see the outlined logic in
http://article.gmane.org/gmane.linux.ports.arm.omap/109233 and
http://article.gmane.org/gmane.linux.ports.arm.omap/109381 ?

Support for regmap access instead of mere MMIO was one of the
things you could do with this approach.  You appear to be in the
situation where you need such an extension (or something similar,
but you really should look into the ll_ops thing).

Thanks for those pointer, I have some reading to do. That seems to
go into the right direction.  What is the status of those patches?
Are they already merged or actively worked on?

Ugh. The ll_ops design is a simplified form of regmap. Why not just use
regmap? It seems like it would be possible to make a regmap per
clk_register_{basic_type}() call via regmap_init_mmio() while still
allowing those functions to take a void __iomem pointer. Then we could
remove clk_readl/clk_writel (after providing *_be variants of the
registration functions for PPC) and just use a regmap throughout the
basic clock type code. Finally we can introduce *_regmap() registration
functions that allow drivers to register basic clock types with regmaps.

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