On Wednesday 05 February 2014, Michal Simek wrote:

On 02/05/2014 10:36 AM, Arnd Bergmann wrote:

quoted

On Wednesday 05 February 2014, Michal Simek wrote:
Still, the choice of putting the timeout into DT in terms of
cycles rather than miliseconds wasn't ideal from an interface
perspective and we should change that if/when we do a generic
binding. I can definitely see where it's coming from for your
case, as the cycle count totally makes sense from an FPGA
tool perspective...

Thanks. I take this like ACK for this current binding description.

Yes, please add my 'Acked-by'.

	Arnd