Hi Arnd,

sorry for the delay. I'll rework the driver to include some ideas
proposed by you and Boris. Boris proposed to have several timing
decoders (a generic one, one for NAND and so on). I plan to use the
compatibility name to select the decoder.and use the DT representation
you proposed last : one top "simple-bus" and one sub-node "atmel,smc"
per chip-select with one (or more) sub-device per chip-select.

Jean-Jacques




2014/1/2 Arnd Bergmann [off-list ref]:

On Thursday 02 January 2014 20:31:00 Jean-Jacques Hiblot wrote:

quoted

quoted

If each bus interface has a fixed range of registers, you can actually
collapse the upper two nodes again and just have one device per
chipselect.

This is indeed the case, but I'd rather keep the top node to highlight
the fact that all the devices are physically tied to the same bus.

How about using a top-level "simple-bus" node with the complex ranges
property but making the driver match the sub-devices with the smaller
register range then?

        Arnd

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