[PATCH 1/3] arm: socfpga: Set the SDMMC clock phase in system manager

Hi Chris,

On Sep 25, 2013, at 8:50 PM, Chris Ball wrote:

Hi Dinh,

On Sat, Sep 14 2013, Pavel Machek wrote:

quoted

quoted

From: Dinh Nguyen <redacted>

Add functionality in the System Manager to set the SDR settings for the
SD/MMC IP.

Signed-off-by: Dinh Nguyen <redacted>
Cc: Pavel Machek <redacted>

quoted

+void socfpga_sysmgr_set_dwmmc_drvsel_smpsel(void)
+{
+	struct device_node *np;
+	u32 timing[2];
+	u32 hs_timing;
+
+	np = of_find_compatible_node(NULL, NULL, "altr,socfpga-dw-mshc");
+	of_property_read_u32_array(np, "samsung,dw-mshc-sdr-timing", timing, 2);
+	hs_timing = SYSMGR_SDMMC_CTRL_SET(timing[0], timing[1]);
+	writel(hs_timing, sys_manager_base_addr + SYSMGR_SDMMCGRP_CTRL_OFFSET);
+}
+EXPORT_SYMBOL(socfpga_sysmgr_set_dwmmc_drvsel_smpsel);

To get the abstraction right, would it make sense to have timing
parameters as arguments to socfpga_sysmgr_set_dwmmc_drvsel_smpsel(),
so that sysmgr code is not walking MMC's device tree directly?

I think this review comment from Pavel is still open, please reply.

I sent a Rev 2 that addresses this comment on 9/23. Let me know if I need to resend it in case you missed it.

Thanks,
Dinh

Thanks,

- Chris.
-- 
Chris Ball   [off-list ref]   <http://printf.net/>