On Sun, Sep 29, 2013 at 01:34:08AM -0300, Emilio L?pez wrote:

quoted

quoted

Also, would any special considerations be needed when adjusting the
ahb clock? A future cpufreq driver will most likely need to.

While this will be needed at some point, I don't really see how to
handle that properly. The clock framework doesn't seem to have any
callback when it comes to reconfiguring a clock that a device might
use.

Maybe we should consider using one of the other timers; from a quick
look at the A20 user manual, it seems they can run at ~200MHz
("PLL6/6" as input)

Which timers are you talking about? I only find the usual timers we
already have support for and the timers supported in this user manual.

quoted

This will also creates trouble for IPs such as the I2C that have to
setup internal dividers, and use clk_get_rate to do so.

Not really, because they use APB1 which is not scaled. The manual
makes it explicit when describing APB1:

"This clock is used for some special module apbclk(twi,uart,
ps2, can, scr). Because these modules need special clock rate
even if the apbclk changed."

Hmmm, right. But still, we can have IPs that depend on this one that
requires to readjust their internal rate whenever AHB is recalculated.
These HS timers for example :)

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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