On Thu, Aug 08, 2013 at 05:38:33PM +0200, Stephen Warren wrote:

On 08/07/2013 11:55 PM, Mark Zhang wrote:

quoted

Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30.
So correct the parents and mux width for them.

Acked-by: Stephen Warren <redacted>

Acked-by: Peter De Schrijver <redacted>

Note that in downstream we intentionally leave out pllc2 and pllc3 as possible
parents for clocks which are not controlled using the cbus/shared clock
mechanism.

Cheers,

Peter.