[PATCH 2/2] clk/zynq/pll: Use #defines for fbdiv min/max values
From: joe@perches.com (Joe Perches)
Date: 2013-07-19 19:12:14
Also in:
lkml
On Fri, 2013-07-19 at 10:16 -0700, Soren Brinkmann wrote:
Use more descriptive #defines for the minimum and maximum PLL feedback divider.
trivial
quoted hunk
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
[]
quoted hunk
@@ -63,10 +66,10 @@ static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, u32 fbdiv; fbdiv = DIV_ROUND_CLOSEST(rate, *prate); - if (fbdiv < 13) - fbdiv = 13; - else if (fbdiv > 66) - fbdiv = 66; + if (fbdiv < PLL_FBDIV_MIN) + fbdiv = PLL_FBDIV_MIN; + else if (fbdiv > PLL_FBDIV_MAX) + fbdiv = PLL_FBDIV_MAX;
clamp