@@ -39,6 +39,7 @@
 static u32 pit_cycle;		/* write-once */
 static u32 pit_cnt;		/* access only w/system irq blocked */
 static void __iomem *pit_base_addr __read_mostly;
+static struct clk *mck;
 
 static inline unsigned int pit_read(unsigned int reg_offset)
 {

@@ -186,6 +187,7 @@ static int __init of_at91sam926x_pit_init(void)
 {
 	struct device_node	*np;
 	int			ret;
+	int			err = -EINVAL;
 
 	np = of_find_matching_node(NULL, pit_timer_ids);
 	if (!np)

@@ -195,10 +197,19 @@ static int __init of_at91sam926x_pit_init(void)
 	if (!pit_base_addr)
 		goto node_err;
 
+	mck = of_clk_get(np, 0);
+	if (IS_ERR(mck)) {
+		err = PTR_RET(mck);
+		mck = NULL;
+		pr_crit("AT91: PIT: Unable to get mck clk from DT\n");
+		goto ioremap_err;
+	}
+
 	/* Get the interrupts property */
 	ret = irq_of_parse_and_map(np, 0);
 	if (!ret) {
 		pr_crit("AT91: PIT: Unable to get IRQ from DT\n");
+		clk_put(mck);
 		goto ioremap_err;
 	}
 	at91sam926x_pit_irq.irq = ret;

@@ -212,7 +223,7 @@ ioremap_err:
 node_err:
 	of_node_put(np);
 err:
-	return -EINVAL;
+	return err;
 }
 #else
 static int __init of_at91sam926x_pit_init(void)

@@ -237,7 +248,13 @@ void __init at91sam926x_pit_init(void)
 	 * Use our actual MCK to figure out how many MCK/16 ticks per
 	 * 1/HZ period (instead of a compile-time constant LATCH).
 	 */
-	pit_rate = clk_get_rate(clk_get(NULL, "mck")) / 16;
+	if (!mck)
+		mck = clk_get(NULL, "mck");
+
+	if (IS_ERR(mck))
+		panic("AT91: PIT: Unable to get mck clk\n");
+	pit_rate = clk_get_rate(mck) / 16;
+	pr_notice("AT91: PIT: mck rate = %lu\n", pit_rate);
 	pit_cycle = (pit_rate + HZ/2) / HZ;
 	WARN_ON(((pit_cycle - 1) & ~AT91_PIT_PIV) != 0);