On Sat, Feb 23, 2013 at 05:59:33AM +0100, Joseph Lo wrote:

On Sat, 2013-02-23 at 12:32 +0800, Stephen Warren wrote:

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On 02/22/2013 07:38 PM, Joseph Lo wrote:

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On Fri, 2013-02-22 at 21:00 +0800, Peter De Schrijver wrote:

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On Fri, Feb 22, 2013 at 07:44:49AM +0100, Joseph Lo wrote:

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Adding the power on function for secondary CPUs in PMC driver, this can
help us to remove legacy powergate driver and add generic power domain
support later.

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diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c

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+static u8 tegra_cpu_domains[] = {
+	0xFF,			/* not available for CPU0 */

On Tegra114 we can also powergate CPU0, so this needs to be defined then.

No, DON'T DO THAT!!
We don't allow any code to power gate CPU0 manually here or elsewhere.

The function here only for SMP and hotplug bring up for secondary CPU.

Doesn't Tegra114 have improved HW that does actually allow
power-gating/hot-unplugging/... CPU 0, even though older HW didn't?

Indeed. It support CPU0 be power gated. But the power up sequence does
not through here by toggling PMC directly. Just like the CPU idle
"powered-down" mode. The CPU0's power gating/un-gating sequence should
set up some event flags in flow-controller and controlled by
flow-controller.

Yes, obviously. We don't use this for powergating cores normally...
Sorry for the confusion.

Cheers,

Peter.