ARM coherent allocs, Was: ixp4xx eth broken in 3.7.0/3.8-rc5?

Mikael Pettersson [off-list ref] writes:

 > I'm not sure how is it supposed to work. Environment: IXP4xx CPU,
 > only 64 MB (of 256 MB) of RAM is available for PCI bus master DMA,
 > /dev/sda is a PATA CF or SATA SSD using CS5536-based PATA interface
 > (SATA - with a bridge) in DMA (PCI bus master) mode.
 >
 > It works in PIO mode.
 > The problem seems to be this: pci_dev->dev.coherent_dma_mask is 0x3FFFFFF
 > (64MB-1). Yet __dma_alloc() called with GFP_DMA returns memory
 > physically located (dma_handle) above 64MB region.

Isn't that what the ARM-specific dma bounce allocator is supposed to
handle?  Or did e9da6e9905e639b0f842a244bc770b48ad0523e9 disable that
one?

The so called "coherent" (aka "consistent") allocations mean that both
CPU and other bus masters can read and write at will, (almost) no
synchronization is needed and no map/unmap/sync calls are issued. This
also means the bounce buffering can't be used.
Streaming allocs (which can bounce) use "dma_mask" and coherent allocs
use "coherent_dma_mask".

My ixp4xx box only has 64MB RAM so there is never any bouncing there,
in fact I patch my kernel to disable the bounce support entirely.

Right. The problem is only visible with more than 64 MB RAM.
-- 
Krzysztof Halasa