On Thu, Feb 14, 2013 at 06:30:39PM +0100, Stephen Warren wrote:
On 02/14/2013 03:01 AM, Peter De Schrijver wrote:
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On Wed, Feb 13, 2013 at 05:48:03PM +0100, Stephen Warren wrote:
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You still need to initialize all the UART clocks in init_table[]. This
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Yes. The parent relationships still need to be defined. But I think that's
the only thing we actually need to define still?
You might want to explicitly set the rate too, if there is a divider in
the clk module that affects it. If not, then parenting is indeed all you
need.
Yes, for PLLs that might be useful. Device clock rates can also be set by the
driver and probably should be set by the driver.
Cheers,
Peter.