[PATCH] regulator: anatop: improve precision of delay time
From: Mark Brown <hidden>
Date: 2013-02-08 11:15:25
On Mon, Feb 04, 2013 at 10:21:32AM +0800, Shawn Guo wrote:
For cpufreq example, it takes 13 steps (25 mV for one step) to increase vddcore from 0.95 V to 1.275 V, and the time of 64 clock cycles at 24 MHz for one step is ~2.67 uS, so the total delay time would be ~34.71 uS. But the current calculation in the driver gives 39 uS. Change the formula to have the addition of 1 be the last step, so that we can get a more precise delay time. For example above, the new formula will give 35 uS.
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