[PATCH v2 4/6] ARM: davinci: da850: add DT node for eth0.
From: prabhakar.csengg@gmail.com (Prabhakar Lad)
Date: 2013-02-04 05:07:55
Also in:
linux-devicetree, lkml, netdev
Sekhar , On Sun, Feb 3, 2013 at 5:33 PM, Sekhar Nori [off-list ref] wrote:
On 1/28/2013 7:17 PM, Prabhakar Lad wrote:quoted
From: Lad, Prabhakar <redacted> Add eth0 device tree node information and pinmux for mii to da850 by providing interrupt details and local mac address of eth0. Signed-off-by: Lad, Prabhakar <redacted> Cc: linux-arm-kernel at lists.infradead.org Cc: linux-kernel at vger.kernel.org Cc: davinci-linux-open-source at linux.davincidsp.com Cc: netdev at vger.kernel.org Cc: devicetree-discuss at lists.ozlabs.org Cc: Sekhar Nori <redacted> Cc: Heiko Schocher <redacted> --- arch/arm/boot/dts/da850-evm.dts | 5 +++++ arch/arm/boot/dts/da850.dtsi | 35 +++++++++++++++++++++++++++++++++++ 2 files changed, 40 insertions(+), 0 deletions(-)diff --git a/arch/arm/boot/dts/da850-evm.dts b/arch/arm/boot/dts/da850-evm.dts index a319491..19aa2b3 100644 --- a/arch/arm/boot/dts/da850-evm.dts +++ b/arch/arm/boot/dts/da850-evm.dts@@ -30,6 +30,11 @@ mdio: davinci_mdio at 1e24000 { status = "okay"; }; + eth0: emac at 1e20000 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mii_pins>; + }; }; nand_cs3 at 62000000 { status = "okay";diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi index ba28f2d..76905f3 100644 --- a/arch/arm/boot/dts/da850.dtsi +++ b/arch/arm/boot/dts/da850.dtsi@@ -56,6 +56,26 @@ 0x30 0x01100000 0x0ff00000 >; }; + mii_pins: pinmux_mii_pins { + pinctrl-single,bits = < + /* + * MII_TXEN, MII_TXCLK, MII_COL + * MII_TXD_3, MII_TXD_2, MII_TXD_1 + * MII_TXD_0 + */ + 0x8 0x88888880 0xfffffff0 + /* + * MII_RXER, MII_CRS, MII_RXCLK + * MII_RXDV, MII_RXD_3, MII_RXD_2 + * MII_RXD_1, MII_RXD_0 + */ + 0xc 0x88888888 0xffffffff + /* MDIO_CLK, MDIO_D */You call this mii_pins, but include mdio pins in there as well. Can you separate them out? Then some board which uses rmii can simply reuse the entry.
Ok makes sense.
quoted
+ 0x10 0x00222288 0x00ffffff + /* GPIO2_6 */ + 0x18 0x00000080 0x000000f0This is SoC specific pin list. Such board specific pins should not make it here.
Ok, so this should be set up using GPIO API's ?
quoted
+ >; + }; }; serial0: serial at 1c42000 { compatible = "ns16550a";@@ -88,6 +108,21 @@ reg = <0x224000 0x1000>; bus_freq = <2200000>; }; + eth0: emac at 1e20000 { + compatible = "ti,davinci-dm6467-emac"; + reg = <0x220000 0x4000>; + ti,davinci-ctrl-reg-offset = <0x3000>; + ti,davinci-ctrl-mod-reg-offset = <0x2000>; + ti,davinci-ctrl-ram-offset = <0>; + ti,davinci-ctrl-ram-size = <0x2000>; + local-mac-address = [ 00 00 00 00 00 00 ]; + interrupts = <33 + 34 + 35 + 36 + >; + phy-handle = <&mdio>;I doubt this is required. This property is to pass a handle to the phy, not mdio bus.
Ok I'll check on this. Regards, --Prabhakar
Thanks, Sekhar