[PATCH v2 19/27] pci: PCIe driver for Marvell Armada 370/XP systems
From: Thomas Petazzoni <hidden>
Date: 2013-01-31 15:22:37
Also in:
linux-pci
Dear Russell King - ARM Linux, On Thu, 31 Jan 2013 15:08:01 +0000, Russell King - ARM Linux wrote:
On Thu, Jan 31, 2013 at 03:57:37PM +0100, Thomas Petazzoni wrote:quoted
Indeed. But this function never gets called with bus->number == 0, only with bus->number = 1, 2, 3, 4, 5, 6. So those are child busses, and therefore they have a parent.Having thought about it, yes, that's what I expect, because root bus resources are never resized. Root bus resources are normally setup before probing to indicate what size they _can_ be and define what space is available to the downstream devices. Child busses (behind a PCI-2-PCI bridge) are a different matter - these will be adjusted according to their on-bus devices and the windows for them sized and allocated appropriately _within_ the confines of the root bus resource.
Ok.
quoted
I am talking about the PCI-to-PCI bridges. I want the I/O windows assigned to each PCI-to-PCI bridge to be 64K aligned. The PCI-to-PCI bridges are devices that sit on bus 0, each giving access to the child buses 1, 2, 3, 4, 5, 6.Right, so you've just confirmed that this _is_ the right hook and it _is_ being called at the right time.
Ok.
However, I had interpreted your requirement as the _host_ bridge only (insufficient information in your previous emails, or I missed it).
Might be insufficient information, or wrong terminology on my side.
If that's what your bridge requires, then we need to detect it via its vendor and device IDs and only apply this fixup to those bridges which require a 64K alignment. So, the IDs are vendor:device = 0x11ab:0x1092 ? And let me get this straight, it _is_ a specific requirement for this particular bridge P2P bridge?
The vendor/device ID will change. This P2P bridge is emulated. However, I'm not sure why you need to know the vendor:device ID to make the fixup specific. The fixup is already specific to those bridges, since I am just setting pci_sys_data->win_align_io to 64K for the particular buses that are downstream the problematic bridges. So it doesn't affect any other bus on the system, and therefore I don't think this fixup needs to be made specific to a given vendor:device, no? Best regards, Thomas -- Thomas Petazzoni, Free Electrons Kernel, drivers, real-time and embedded Linux development, consulting, training and support. http://free-electrons.com