[RFC PATCH v2 3/5] ARM: kernel: update cpu_suspend code to use cache LoUIS operations
From: Guennadi Liakhovetski <hidden>
Date: 2012-12-11 17:07:35
Also in:
linux-omap, linux-sh
Hi Will On Tue, 11 Dec 2012, Will Deacon wrote:
On Tue, Dec 11, 2012 at 04:33:13PM +0000, Will Deacon wrote:quoted
On Tue, Dec 11, 2012 at 04:07:56PM +0000, Guennadi Liakhovetski wrote:quoted
Git bisect identified this patch, in the mainline as commit dbee0c6fb4c1269b2dfc8b0b7a29907ea7fed560 Author: Lorenzo Pieralisi [off-list ref] Date: Fri Sep 7 11:06:57 2012 +0530 ARM: kernel: update cpu_suspend code to use cache LoUIS operations as the culprit of the broken wake up from STR on mackerel, based on an sh7372 A8 SoC. .config attached.My guess is that because Cortex-A8 does not implement the MP extensions, the LoUIS field of the CLIDR reads as zero, and the cache isn't flushed at all (I can see an early exit in v7_flush_dcache_louis). Lorenzo -- how is this supposed to work for uniprocessor CPUs?Bah, forgot to ask you if the following patch helps...
Yes, it does. Thanks Guennadi
quoted hunk ↗ jump to hunk
Will --->8diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index cd95664..f58248f 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S@@ -44,7 +44,8 @@ ENDPROC(v7_flush_icache_all) ENTRY(v7_flush_dcache_louis) dmb @ ensure ordering with previous memory accesses mrc p15, 1, r0, c0, c0, 1 @ read clidr, r0 = clidr - ands r3, r0, #0xe00000 @ extract LoUIS from clidr + ALT_SMP(ands r3, r0, #(7 << 21)) @ extract LoUIS from clidr + ALT_UP(ands r3, r0, #(7 << 27)) @ extract LoUU from clidr mov r3, r3, lsr #20 @ r3 = LoUIS * 2 moveq pc, lr @ return if level == 0 mov r10, #0 @ r10 (starting level) = 0
--- Guennadi Liakhovetski, Ph.D. Freelance Open-Source Software Developer http://www.open-technology.de/