Thread (38 messages) flat view 38 messages, 9 authors, 2012-12-11
STALE4987d

Revision rfc of 7 in this series.

Revisions (7)
  1. rfc [diff vs current]
  2. rfc [diff vs current]
  3. rfc [diff vs current]
  4. rfc [diff vs current]
  5. rfc current
  6. rfc [diff vs current]
  7. v2 [diff vs current]

[RFC PATCH 0/2] Add support for a fake, para-virtualised machine

From: Will Deacon <hidden>
Date: 2012-12-05 15:07:32

On Wed, Dec 05, 2012 at 02:52:57PM +0000, Catalin Marinas wrote:
On 4 December 2012 18:14, Will Deacon [off-list ref] wrote:
quoted
Well, this depends on the guest taking an undefined instruction exception on
the smc, then deciding to issue an hvc instead and *then* having the
hypervisor somehow translate that into a PSCI invocation. It could work, but
it sounds easy to mess up and relies on the PSCI firmware co-existing with
things like kvm.
We can have enable-method DT entries independent of the SoC and one of
them can be psci-hvc.
As soon as the support is there in the upper layers, we can do that.
Just for clarification, AArch32 with virtualisation mandates the
security extensions, so the SMC can be trapped. On AArch64 it is a bit
tricky since the presence of EL3 is not mandate, in which case SMC
would undef (don't as why ;). That's where we can have different
enable methods specified via the DT.
Not entirely true: only ARMv7 mandates the security extensions in this
manner. You can still have ARMv8 CPUs running AArch32 code without the
security extensions.

Will
Keyboard shortcuts
hback out one level
jnext message in thread
kprevious message in thread
ldrill in
Escclose help / fold thread tree
?toggle this help