[PATCH] ARM: decompressor: clear SCTLR.A bit for v7 cores
From: Nicolas Pitre <hidden>
Date: 2012-11-05 20:02:51
On Mon, 5 Nov 2012, Rob Herring wrote:
On 11/05/2012 11:26 AM, Dave Martin wrote:quoted
On Mon, Nov 05, 2012 at 11:13:51AM -0500, Nicolas Pitre wrote:quoted
On Mon, 5 Nov 2012, Russell King - ARM Linux wrote:quoted
On Mon, Nov 05, 2012 at 01:02:55PM +0000, Dave Martin wrote:quoted
Why not allow unaligned accesses in the decompressor, though, both for v6 and v7?EXACTLY.I have no objections to that. In fact, I made a remark to this effect in my initial review of this patch. Whether or not gcc does take advantage of this hardware ability in the end is orthogonal.For the sake of argument, here's how it might look. Currently, I make no attempt to restore the original state of the U bit. The A bit if forced later by the kernel during boot, after a short window during which we should only run low-level arch code and therefore where no unaligned accesses should happen. Does anyone think these issues are likely to be important?And here is my updated version that does v6 somewhat differently:
If I had to choose, I'd prefer Dave's version as being a bit cleaner.
quoted hunk ↗ jump to hunk
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From 76c2b7685397f13aa53f426822128430fc24b8a0 Mon Sep 17 00:00:00 2001From: Rob Herring <redacted> Date: Mon, 5 Nov 2012 11:39:48 -0600 Subject: [PATCH v2] ARM: decompressor: clear SCTLR.A bit for v6 and v7 cores With recent compilers and move to generic unaligned.h in commit d25c881 (ARM: 7493/1: use generic unaligned.h), unaligned accesses will be used by the LZO decompressor on v7 cores. So we need to make sure unaligned accesses are allowed by clearing the SCTLR A bit. While v6 can support unaligned accesses, it is optional and current compilers won't emit unaligned accesses. In case this changes and to align with the kernel behavior, we clear the A bit and set the U bit. Signed-off-by: Rob Herring <redacted> Acked-by: Nicolas Pitre <redacted> Tested-by: Shawn Guo <redacted> --- arch/arm/boot/compressed/head.S | 6 ++++++ 1 file changed, 6 insertions(+)diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S index bc67cbf..f14d7ec 100644 --- a/arch/arm/boot/compressed/head.S +++ b/arch/arm/boot/compressed/head.S@@ -629,6 +629,11 @@ __armv4_mmu_cache_on: mcr p15, 0, r0, c7, c10, 4 @ drain write buffer mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs mrc p15, 0, r0, c1, c0, 0 @ read control reg + mrc p15, 0, r11, c0, c0 @ get processor ID + and r11, r11, #0xf0000 + tst r11, #0x70000 @ ARMv6 + orreq r0, r0, #1 << 22 @ set SCTLR.U + biceq r0, r0, #1 << 1 @ clear SCTLR.A orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x0030 #ifdef CONFIG_CPU_ENDIAN_BE8@@ -654,6 +659,7 @@ __armv7_mmu_cache_on: #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg bic r0, r0, #1 << 28 @ clear SCTLR.TRE + bic r0, r0, #1 << 1 @ clear SCTLR.A orr r0, r0, #0x5000 @ I-cache enable, RR cache replacement orr r0, r0, #0x003c @ write buffer #ifdef CONFIG_MMU-- 1.7.10.4