Thread (12 messages) flat view 12 messages, 6 authors, 2012-11-19

[PATCH 1/2] clk: mvebu: armada 370/XP add clock gating control provider for DT

From: andrew@lunn.ch (Andrew Lunn)
Date: 2012-11-17 08:26:14
Also in: lkml

Hi Gregory

Nice work

On Fri, Nov 16, 2012 at 07:01:59PM +0100, Gregory CLEMENT wrote:
quoted hunk ↗ jump to hunk
Signed-off-by: Gregory CLEMENT <redacted>
---
 .../bindings/clock/mvebu-gated-clock.txt           |   43 ++++++++++++++
 arch/arm/mach-mvebu/Kconfig                        |    1 +
 drivers/clk/mvebu/clk-gating-ctrl.c                |   61 ++++++++++++++++++++
 3 files changed, 105 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
index 7497cc0..9dbcdd9 100644
--- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
+++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
@@ -6,6 +6,49 @@ the clock ID in its "clocks" phandle cell. The clock ID is directly mapped to
 the corresponding clock gating control bit in HW to ease manual clock lookup
 in datasheet.
 
+The following is a list of provided IDs for Armada XP:
Should that the 370, not XP?
+ID	Clock	Peripheral
+-----------------------------------
+0	Audio	AC97 Cntrl
+1	pex0_en	PCIe 0 Clock out
+2	pex1_en	PCIe 1 Clock out
+3	ge1	Gigabit Ethernet 1
+4	ge0	Gigabit Ethernet 0
+5	pex0	PCIe Cntrl 0
+9	pex1	PCIe Cntrl 1
+15	sata0	SATA Host 0
+17	sdio	SDHCI Host
+25	tdm	Time Division Mplx
+28	ddr	DDR Cntrl
+30	sata1	SATA Host 0
Not many clocks there. USB? XOR? Crypto?

What is the ddr clock for? Does bad things happen if you turn it off?
Kirkwood has a similar clock, dunit, which i decided not to export,
since when you turn it off, the whole SoC locks up.

Thanks
      Andrew
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