Question about ION carveout heap support partial cache flush

On Mon, Aug 27, 2012 at 4:29 PM, Russell King - ARM Linux
[off-list ref] wrote:

On Mon, Aug 27, 2012 at 04:23:31PM +0800, zhangfei gao wrote:

quoted

On Mon, Aug 27, 2012 at 1:46 PM, Haojian Zhuang
[off-list ref] wrote:

quoted

Let me summerize it. First, user space address is mapped. Then,
flushing user space
address is triggered. It's a workaround of fixing non-existed virtual
address without fixing
vmap() or any other solution. It's just a quick fix.

Zhangfei,
I doubt that the issue may be caused by missing memory barrier.
Flushing is using
coprocessor instructions. It's a little different.

Is there any limitation that dmac_map_area & dmac_flush_range
supporting addr mapped from user space?

They DEFINITELY DO NOT SUPPORT FLUSHING USER SPACE.

Thanks Russell

Any suggestion of flushing cache according to cache line, instead of PAGE_SIZE.
In order to get specific area, we use addr from user directly, which
may not be the PAGE start.

We have some usage case to flush cache according to cache line.
CPU - cache - ddr - gpu
1. For correctness, driver only flush used size, if align to PAGE_SIZE,
other area may be flushed by mistake.
2. for efficiency, cache line align will be perfered.

Thanks