[PATCH] ARM: mxc: ssi-fiq: Make ssi-fiq.S Thumb-2 compatible

On Tue, Aug 14, 2012 at 6:40 AM, Sascha Hauer [off-list ref] wrote:

On Mon, Aug 13, 2012 at 05:28:17PM -0500, Matt Sealey wrote:

quoted

 IMX_PIN_REG(MX51_PAD_EIM_DA15, NO_PAD, 0x058, 0, 0x000, 0), /*
MX51_PAD_EIM_DA15__EIM_DA15 */



On Mon, Aug 13, 2012 at 2:35 PM, Sascha Hauer [off-list ref] wrote:

quoted

Hi Dave,

On Fri, Aug 10, 2012 at 12:53:24PM +0100, Dave Martin wrote:

quoted

Because FIQ handlers get copied straight into the vectors page to
the FIQ vector entry point, FIQ handlers in a Thumb-2 kernel must
start in Thumb-2.  A Thumb-2 kernel enters all exception vectors in
Thumb-2.

I finally came along testing this. I have no Thumb2 capable hardware
to test if it works in thumb2 mode, but at least in Arm mode it works.
This is enough to not introduce a regression, so we can go for this.

This is the interesting dichotomy; the code is only required truly on
devices where Thumb2 isn't available, right?

It is also used on the i.MX51 Eukrea board. I asked Eric (Cced) to test
it in thumb2 mode, no response so far. I don't know the reason why he
uses FIQ mode instead of SDMA, maybe simply historical reasons.

If we can lose that requirement then the only thing in the way is the
phyCORE support, which goes away on a "pure" v7 config anyway,
correct? I was just thinking, why not split v6_v7_defconfig into a
v7_defconfig losing those boards anyway and enable Thumb2 by default
while we're at it? It would mean more testing gets done and this error
would crop up both more often, but be less surprising and won't take a
year to revisit ;)

Pure v7 config would still include Tegra, OMAP3/4, i.MX5 onwards and
the newer chips. One zImage for v6_v7 is still possible but I don't
know if anyone really has the idea in their heads that you'd want to
boot the same kernel on i.MX3 as well as i.MX6Q even if they do share
drivers to some degree.

-- 
Matt Sealey [off-list ref]
Product Development Analyst, Genesi USA, Inc.