[PATCH 1/2] ARM: imx: enable emi_slow_gate clock for imx5
From: s.hauer@pengutronix.de (Sascha Hauer)
Date: 2012-08-03 14:11:08
On Thu, Aug 02, 2012 at 11:01:51PM +0800, Shawn Guo wrote:
The imx5 common clock migration causes a regression with smsc911x driver on imx53-ard board, where a smsc lan9220 controller gets connected on imx53 with EIM interface. EIM needs clock emi_slow_gate to be functional. In the new imx5 clock driver, there is no use count incremented for the clock by enabling it, so the framework closes the clock at late init time and makes EIM stop working then. Enable emi_slow_gate in clock driver initialization to fix the regression.
Can we add a comment that emi_slow_gate is needed for the EIM interface? It's not obvious from the datasheet and this information might help people who want to clean up the now unconditionally enabled clocks. Otherwise: Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Sascha
quoted hunk ↗ jump to hunk
Cc: stable at vger.kernel.org Signed-off-by: Shawn Guo <redacted> --- arch/arm/mach-imx/clk-imx51-imx53.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c index f608669..6eee32a 100644 --- a/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/arch/arm/mach-imx/clk-imx51-imx53.c@@ -303,6 +303,7 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk_prepare_enable(clk[aips_tz2]); /* fec */ clk_prepare_enable(clk[spba]); clk_prepare_enable(clk[emi_fast_gate]); /* fec */ + clk_prepare_enable(clk[emi_slow_gate]); clk_prepare_enable(clk[tmax1]); clk_prepare_enable(clk[tmax2]); /* esdhc2, fec */ clk_prepare_enable(clk[tmax3]); /* esdhc1, esdhc4 */-- 1.7.5.4
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