[PATCH v3 04/10] ARM: tegra: Move tegra_pcie_xclk_clamp() to PMC
From: Thierry Reding <hidden>
Date: 2012-07-26 19:55:06
Also in:
linux-devicetree, linux-pci, linux-tegra
Subsystem:
arm port, the rest · Maintainers:
Russell King, Linus Torvalds
The PMC code already accesses to PMC registers so it makes sense to move this function there as well. While at it, rename the function to tegra_pmc_pcie_xclk_clamp() for consistency. Signed-off-by: Thierry Reding <redacted> Acked-by: Stephen Warren <redacted> --- Changes in v3: - none Changes in v2: - none arch/arm/mach-tegra/pcie.c | 30 ++++-------------------------- arch/arm/mach-tegra/pmc.c | 16 ++++++++++++++++ arch/arm/mach-tegra/pmc.h | 1 + 3 files changed, 21 insertions(+), 26 deletions(-)
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
index 576347a..efe71dd 100644
--- a/arch/arm/mach-tegra/pcie.c
+++ b/arch/arm/mach-tegra/pcie.c@@ -42,6 +42,7 @@ #include <mach/powergate.h> #include "board.h" +#include "pmc.h" /* register definitions */ #define AFI_OFFSET 0x3800
@@ -145,17 +146,6 @@ #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20) #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20) -/* PMC access is required for PCIE xclk (un)clamping */ -#define PMC_SCRATCH42 0x144 -#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) - -static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); - -#define pmc_writel(value, reg) \ - __raw_writel(value, reg_pmc_base + (reg)) -#define pmc_readl(reg) \ - __raw_readl(reg_pmc_base + (reg)) - /* * Tegra2 defines 1GB in the AXI address map for PCIe. *
@@ -647,18 +637,6 @@ static int tegra_pcie_enable_controller(void) return 0; } -static void tegra_pcie_xclk_clamp(bool clamp) -{ - u32 reg; - - reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; - - if (clamp) - reg |= PMC_SCRATCH42_PCX_CLAMP; - - pmc_writel(reg, PMC_SCRATCH42); -} - static void tegra_pcie_power_off(void) { tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
@@ -666,7 +644,7 @@ static void tegra_pcie_power_off(void) tegra_periph_reset_assert(tegra_pcie.pex_clk); tegra_powergate_power_off(TEGRA_POWERGATE_PCIE); - tegra_pcie_xclk_clamp(true); + tegra_pmc_pcie_xclk_clamp(true); } static int tegra_pcie_power_regate(void)
@@ -675,7 +653,7 @@ static int tegra_pcie_power_regate(void) tegra_pcie_power_off(); - tegra_pcie_xclk_clamp(true); + tegra_pmc_pcie_xclk_clamp(true); tegra_periph_reset_assert(tegra_pcie.pcie_xclk); tegra_periph_reset_assert(tegra_pcie.afi_clk);
@@ -689,7 +667,7 @@ static int tegra_pcie_power_regate(void) tegra_periph_reset_deassert(tegra_pcie.afi_clk); - tegra_pcie_xclk_clamp(false); + tegra_pmc_pcie_xclk_clamp(false); clk_prepare_enable(tegra_pcie.afi_clk); clk_prepare_enable(tegra_pcie.pex_clk);
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index 7af6a54..399dc3a 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c@@ -24,6 +24,10 @@ #define PMC_CTRL 0x0 #define PMC_CTRL_INTR_LOW (1 << 17) +/* PMC access is required for PCIE xclk (un)clamping */ +#define PMC_SCRATCH42 0x144 +#define PMC_SCRATCH42_PCX_CLAMP (1 << 0) + static inline u32 tegra_pmc_readl(u32 reg) { return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
@@ -74,3 +78,15 @@ void __init tegra_pmc_init(void) val &= ~PMC_CTRL_INTR_LOW; tegra_pmc_writel(val, PMC_CTRL); } + +void tegra_pmc_pcie_xclk_clamp(bool clamp) +{ + u32 reg; + + reg = tegra_pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP; + + if (clamp) + reg |= PMC_SCRATCH42_PCX_CLAMP; + + tegra_pmc_writel(reg, PMC_SCRATCH42); +}
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4..2631c9a 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h@@ -19,5 +19,6 @@ #define __MACH_TEGRA_PMC_H void tegra_pmc_init(void); +void tegra_pmc_pcie_xclk_clamp(bool clamp); #endif
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1.7.11.2